|
Model name
|
LavaAP40/100GE2P
|
LavaAP40/100GE2RP
|
|
Ports per module
|
- (2) 100GbE CFP MSA
- (2) 40GbE CFP MSA or (4) 40GbE QSFP+ [with interface adapter]
- (2) 100GbE CXP [with interface adapter]
- (2) 100GbE QSFP28 [with interface adapter]
|
|
Chassis slots per module
|
1
|
1
|
|
Maximum ports per chassis
|
- XGS12-SD 12-slot rackmount:
- (24) 100GbE CFP MSA or (48) 40GbE QSFP+, (12) CXP, (12) QSFP28
- XGS12-HS 12-slot rackmount:
- (24) 100GbE CFP MSA or (48) 40GbE QSFP+, (12) CXP, (12) QSFP28
- XG12 12-slot rackmount:
- (24) 100GbE CFP MSA or (48) 40GbE QSFP+, (12) CXP, (12) QSFP28
- XGS2-SD 2-slot:
- (4) 100GbE CFP MSA or (8) 40GbE QSFP+, (4) CXP, (4) QSFP28
- XGS2-HS 2-slot:
- (4) 100GbE CFP MSA or (8) 40GbE QSFP+, (4) CXP, (4) QSFP28
- XM2 2-slot benchtop:1
- (2) 100GbE or 40GE CFP MSA or (4) 40GbE QSFP+, (2) CXP, (2) QSFP28
|
|
Transceiver support
|
- CFP MSA 1.4, pluggable MMF and SMF optical transceivers
- SFF-8436 QSFP+, pluggable, and fiber/copper cables (passive/active) with the QSFP+ interface adapter
- CXP MMF optical transceivers and passive, direct attach copper (DAC) cable media with the CXP interface adapter
- The QSFP28 interface adapter supports a multimode Active Optical Cable only. See note for the 948-0029 adapter in the Ordering Section of this document for specific restrictions on the use of this adapter.
|
|
CFP interface adapters
|
- 2-port, CFP-to-QSFP+ for 40GbE operation
- 1-port CFP-to-CXP for 100GbE operation
- 1-port CFP-to-QSFP28 for 100GbE operation. See note for the 948-0029 adapter in the Ordering Section of this document for specific restrictions on the use of this adapter.
|
|
Hardware capture buffer per port
|
1.4GB
|
1.4GB
|
|
Interface protocols
|
- 40-Gigabit Ethernet 40GBASE-R,100-Gigabit Ethernet 100GBASE-R, per IEEE802.3ba-2010 standard
- 100GBASE-SR4 per IEEEP802.3bm-2015 standard (i.e. CFP-to-QSFP28 adapter). See note for the 948-0029 adapter in the Ordering Section of this document for specific restrictions on the use of this adapter.
|
|
Layer 2/3 routing protocol emulation
|
- Comprehensive coverage of routing, MPLS, VPLS, high-availability, IP multicast, switching, Data Center/SDN, Carrier Ethernet, and authentication
- The Accelerated Performance load module supports ultra-high scale and performance for routing protocol emulation per port
- Host/client protocol support: ARP, NDP, ICMP (PING), IPv4, and IPv6
|
- Comprehensive coverage of routing, MPLS, VPLS, high-availability, IP multicast, switching, Data Center/SDN, Carrier Ethernet, and authentication
- The Reduced Performance load module supports up to 100 routing protocol emulation sessions and up to 2,000 broadband access emulation sessions per port
- Host/client protocol support: ARP, NDP, ICMP (PING), IPv4, and IPv6
|
|
Layer 4-7 application traffic testing
|
Yes, with IxLoad support for HTTP, SSL, FTP/TFTP, email (SMTP, POP3, IMAP), IPv4, IPv6, VLAN, ER and AppLibrary for IxNetwork
|
No
|
|
Transmit flows per port
(sequential values)
|
Billions
|
Billions
|
|
Transmit flows per port
(arbitrary values)
|
1 million
|
1 million
|
|
Trackable receive flows per port
|
1 million
|
1 million
|
|
Stream definitions per port
|
512
In packet stream (sequential) or advanced stream (interleaved) mode, each stream definition can generate millions of unique traffic flows
|
|
Table UDF entries
|
512K
Comprehensive packet editing function for emulating large numbers of sophisticated flows. Entries of up to 256 bytes, using lists of values, can be specified and placed at designated offsets within a stream. Each list consists of an offset, a size, and a list of values in a table format.
|
|
Packet flow statistics
|
Track over 1 million flows
|
|
Transmit engine
|
Wire-speed packet generation with timestamps, sequence numbers, data integrity signature, and packet group signatures
|
|
Receive engine
|
Wire-speed packet filtering, capturing, real-time latency and inter-arrival time for each packet group, data integrity, and sequence checking
|
|
User defined field features
|
Fixed, increment or decrement by user-defined step, value list, cascade, random, and chained
|
|
Filters
|
48-bit source/destination address, 2x128-bit user-definable pattern and offset, frame length range, CRC error, data integrity error, sequence checking error (small, big, reverse)
|
|
Statistics and rates (counter size: 64 bits)
|
Link state, line speed, frames sent, valid frames received, bytes sent/received, fragments, undersize, oversize, CRC errors, VLAN tagged frames, 6 user-defined stats, capture trigger (UDS 3), capture filter (UDS 4), user-defined stat 5, user-defined stat 6, 8 QoS counters, data integrity frames, data integrity errors, sequence checking frames, sequence checking errors, ARP, and ping requests and replies
|
|
Error generation
|
CRC (good/bad/none), undersize, oversize
|
|
Latency measurement resolution
|
2.5 nanoseconds and is compatible with all of Ixia’s 10GbE, 1GbE fiber, and 10/100/1000Mbps Ethernet, ATM, and Packet over SONET load modules
|
|
Latency self-calibration
|
Ability to remove inherent latency from 40/100GbE port electronics when used with MSA or SFF-8436-compliant transceivers
|
|
MDIO
|
MDIO v1.4 support is provided for CFP MSA-compliant transceivers
|
|
Transmit line clock adjustment
|
Ability to adjust the parts per million line frequency over a range of
-100 ppm to +100 ppm
|
|
Layer 1 BERT capability
|
The load module supports the following BERT features on both 40GbE and 100GbE speeds:
- User-selected PRBS pattern for each PCS Lane
- User selects from a wide range of PRBS data patterns to be transmitted (true and complement) with the ability to invert the patterns
- Send single, continuous, and exponentially controlled amounts of error injection
- Wide range of statistics, including: Pattern Lock, Pattern Transmitted, Pattern Received, Total Number of Bits Sent and Received, Total Number of Errors Sent and Received, Bit Error Ratio (BER), Number of Mismatched 1’s and 0’s
- Lane Stats Grouping per lambda for SMF and MMF 40GE and 100GE based on IEEE 802.3ba-defined physical medium dependent (PMD)
|
|
40/100GE Physical Coding Sublayer (PCS) test features
|
IEEE 802.3ba-2010 compliant PCS transmit and receive side test capabilities include:
- Per PCS lane, transmit lane mapping - Supports all combination of PCS lane mapping: Default, Increment, Decrement, Random, and Custom.
- Per PCS lane, skew insertion capability - User selectable from zero up to 3 microseconds of PCS Lane skew insertion on the transmit side.
- Per PCS lane, lane marker, or lane marker and payload error injections - User-selectable ability to inject errors into the PCS Lane Marker and simultaneously into PCS Lane Marker and Payload fields. This includes the ability to inject sync bit errors into the Lane Marker and Payload. User can control the PCS lane, number or errors, period count and manage the repetition of the injected errors.
- Per PCS lane, receive lanes statistics - PCS Sync Header and Lane Marker Lock, Lane Marker mapping, Relative lane deskew up to 52 microseconds for 40GE and 104 microseconds for 100GE, Sync Header and PCS Lane Marker Error counters, indicators for Loss of Synch Header and Lane Marker, BIP8 errors.
|
|
IPv4, IPv6, UDP, TCP checksum
|
Hardware checksum generation and verification
|
|
Frame length controls
|
Fixed, random, weighted random, or increment by user-defined step, random, weighted random
|
|
Preamble view
|
Allows the user to select to view and edit the preamble contents
|
|
Link fault signaling
|
Generate local and remote faults with controls for the number of faults and order of faults, plus the ability to select the option to have the transmit port ignore link faults from a remote link partner
|
|
Operating temperature range
|
41°F to 95°F (5°C to 35°C), ambient air[1]
|
|
Load module dimensions
|
16.0” (L) x 12.0” (W) x 1.3” (H)
406mm (L) x 305mm (W) x 33mm (H)
|
|
Weight
|
Module only: 9.8 lbs. (4.45 kg)
Shipping: 12.0 lbs. (5.45 kg)
|
